1. Field of the Invention
This invention relates generally to the electronic package. More particularly, this invention relates to a novel configuration of a package assembly which includes a supporting heat spreader provided with a plurality of saw-teeth to penetrate an adhesive layer covering a plurality of ground planes. These ground contact planes are formed on a backside of a substrate supporting a semiconductor device such that the heat spreader can function as a ground terminal for the semiconductor device. In another preferred embodiment, the heat spreader includes a semiconductor chip placement recess to dispose a semiconductor chip therein thus allowing a substrate to be fabricated with a thickness which is significantly reduced. Again, the heat spreader is made with bottom surface having saw-teeth to contact the ground planes disposed on the backside of the substrate. Improvements in electrical and thermal performance are achieved.
2. Description of the Prior Art
Further improvement of the performance of a packaged integrated circuit (IC) device by employing a ball-grid array (BGA) configuration is limited by the thickness of the substrate. Generally the performance of a BGA package is improved with a substrate of reduced thickness. However, there are several limitations prevent the thickness of the substrate to be further reduced. Conventionally, substrate of multiple layers is employed. The performance of such packages can be improved by reducing the thickness of these layers. However, for a multiple layer substrate, more complicate manufacture processes are required which may involve the processes of punching through holes, the placement of metal traces and wires to different layers, and the arrangement of connecting different signals to wires in different layer all become more complicate. Production costs for packaging is increased while productivity and yield are decreased due to these complexities. On the other hand, the high performance requirements of modern IC devices impose high density of interconnections and large number of input and output signal lines for the IC devices to be packaged into ever-smaller volume. All these design and performance considerations add to the difficulties in attempting to lower the production costs, which are increasing due to the use of a multiple-layer substrate with complicate structures.
For general background information, modern semiconductor packages typically includes a substrate to mount an integrated circuit (IC) chip thereon. The areas on the surface of the substrate next to the mounted chip are then applied to redistribute or fan out the input and output signals from the IC device. The substrate can be a metal, e.g., a copper lead-frame, a laminated epoxy glass, or a ceramic plate. Polymeric encapsulants or plastic molding compounds are used to seal off the device. As the dock speed increases to several hundred megahertz or higher, the speed of signal redistribution impacted by the packaging configurations often becomes a limiting design factor of device performance. Conventional electrical circuit design and packaging technology can no longer satisfy the high-speed signal transmission requirements. For high-speed high performance devices, in order to overcome these performance limitations, there is a demand for improved circuit design and packaging techniques where the signal redistribution processes can be more rapidly and reliably carried out
A technique to simplify the manufacture process and to improve the signal redistribution from the semiconductor device is to form two rings, i.e., a power ring and a ground ring, for wire connection, as that shown in FIGS. 1A and 1B. A perspective view and a cross sectional view for a conventional electronic package 10 for packaging a semiconductor device 20 are shown in FIGS. 1A and 1B respectively. A substrate 12 is attached to a heat sink plate 15 via an adhesive layer 14 to support a semiconductor device 20 placed in a cut-off section 25 disposed in a center portion of the substrate 12. Two rings, i.e., a ground ring 30 and a power ring 35, are formed on the substrate 12 surrounding the semiconductor device 20 disposed in the cut-off section 25. A plurality of conductive wires 40 are interconnected between the semiconductor device 20 and the ground ring 30 and the power ring 35 for connection to a ground voltage or a high or operating voltage. A plurality of signal wires 45 are connected to a corresponding contact pad 50 disposed on the substrate 12 and are further connected to a solder ball 60 via a metal trace 55 formed on the top surface of the substrate 12. The ground ring 30 and the power ring 35 are corrected to a ground plane 65 and a power plane 70 respectively formed beneath the bottom surface of the substrate 12 through a ground via-connection via 75 and a power via connection 80 respectively punched through the substrate 12. The ground plane 65 and the power plane 70 are then interconnected to the balls 60 through another set of via-connections 85 disposed near the peripheral of the substrate 12.
The technique as discussed above is to achieve high performance by forming a multiple layer substrate, including the ground plane 65 and the power plane 70, to increase the interconnection density with higher number of signal traces. Finer metal traces are then applied with smaller spacing between them. Additional through-holes, e.g., via connections 75, 80 and 85, are required to be formed on the substrate for connecting the traces to several layers. The processes required to make a substrate of multiple layer structure and forming a plurality of via-connections cause significant increase in complexity of manufacturing processes and higher production cost for the IC packages. Additionally, the thickness of the substrate 12 as shown in FIG. 1B can not be reduced. It is due to a simple reason that the solder balls 60 are provided in the package to contact the external electrical contacts. The bottom surface of the solder balls 60 must be lower than the bottom of the encapsulate cap 90. The thickness of the semiconductor chip 20 is about 10-15 mils. The encapsulate-cap 90 extends 5 to 10 mils below the chip 20. The thickness of the substrate 12 should be at least 15 to 20 mils, otherwise the bottom of the solder balls 60, which generally have a height of 15 mils, would not be lower than the encapsulate cap 90. Therefore, reduction in substrate thickness, e.g., forming a substrate less than 10 mils, would then causes the encapsulate cap 90 to stick out below the bottom of the solder balls 60. The balls 60 cannot provide the function for external connection to the circuits on the printed circuit board (PCB) for next level integration . This is due to the geometry that the encapsulate 90 now interferes and prevents the solder balls 60 to physically contact the circuits on the printed circuit board (PCB) (not shown) which is to be placed underneath the substrate 12.
Referring now to FIG. 1C for a cross sectional view of another prior art substrate 12' manufactured with a split-wrap-around (SWA) connection configuration attached to a heat spreader 15'. The substrate 12' includes a central cut-off section 25'. The cutoff section 25' provides an open space to allow the bonding wires to interconnect a semiconductor device 20' and the ground and power segments and bonding pads disposed on the downward facing surface of the substrate 12'. Referring also to FIGS. 1D and 1E, along the top surface near the edges of the cut-off portion 25', the substrate 12' has a plurality of mutually insulated contact-pad segments 35'. The mutually insulated contact pad segments 35' are formed to surround the edges of the central cutoff section 25'. Each of these mutually insulated contact-pad segments 35' is connected to a split-wrap-around (SWA) contact edge surface 46'. The SWA contact is formed to wrap around the edge of the cut-off section 25' for connecting the mutually insulated contact-pad segments 35' to a corresponding split plane 19' formed on the bottom surface (referring to FIGS. 1F and 1G). The mutually insulated contact-pad segments 35' and the SWA contact edge surface 46' are preferably in metal films of copper, gold, nickel or other types of conductive metals or combinations of these metals. On the bottom surface of the substrate 12', there are also signal coplanar signal strips 54' formed in the gaps 48' between the coplanar power and ground planes 49. In FIG. 4E, other than the split-wrap-around connection means 46' there are also through hole connection 75' for connecting the contact segments 35' to the split power and ground planes 49' disposed on the bottom surface. This single core double-side substrate provides superior performance and low cost packaging configuration. However, a substrate of greater thickness must be employed. Furthermore, the heat spreader is not connected to provide a ground potential. Further improvements of electric and thermal performance can not be easily achieved due to a thickness requirement of the substrate and a more stable ground potential is not yet provided because the substrate is not electrically connected to the heat spreader.
Therefore, a need still exits in the art to provide a new package assembly with improved electrical performance by reducing the thickness of a substrate and providing more stable ground potential by connecting the substrate to the heat spreader. This new package assembly should improve the performance of the packaged integrated circuit (IC) devices and reduce the production cost of the electronic package with simplified layer structure. It is desirable that the novel configuration of circuit connections employed in the electronic package assembly of this invention can provide less complicate manufacture method such that the production yields and product reliability are also improved. It is also desirable that the heat dissipation of the packaged IC devices can be improved.